Integrated circuit (IC) chips typically include multiple levels of conductive features which are vertically spaced apart and separated by intermediate insulating layers. Interconnections are formed between the levels of conductive features in the chip to provide high wiring density and good thermal performance. The interconnections are formed using lines and vias, which are etched through the insulating layers separating the levels conductive features of the device. Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate, while metal lines run parallel to the semiconductor substrate. The lines and vias are then filled with a conductive material, typically a conductive metal such as copper.
Interconnects are commonly formed through a photolithography process, commonly referred to as a damascene process, that includes the deposition of a patternable masking layer (i.e., “photoresist”). A typical damascene process includes: depositing a dielectric material over a layer containing metal lines (i.e., “Mx layer”); patterning of the dielectric material using photoresist to form via and trench openings; deposition of a conductive material in sufficient thickness to fill the openings to form a via layer (i.e., “Vx layer”) and a contact layer (i.e., “Mx+1 layer”) there over; and removal of the excessive conductive material from an upper surface of the dielectric material using a chemical reactant-based process, mechanical methods, or a combined chemical mechanical polishing (CMP) techniques.
Some damascene techniques, such as trench first damascene, may produce vias that are self-aligned perpendicular to a trench in the Mx+1 layer but not self-aligned in the direction along the trench in the Mx+1 layer. Poor alignment between the vias and the metal lines is due in part to uncontrolled chamfer formation in the vias of the Vx layer. This uncontrolled chamfer formation occurs during etching due to the variability of etch rates and limits of etch precision. Because the chamfered sides of a via extend to an upper surface of a line that is usually in close proximity to another line, uncontrolled via chamfer formation can lead to a sub-optimal or sub-critical distance between a non-corresponding via and line. In some cases, the via may actually be in contact with the non-corresponding metal line. A sub-optimal or sub-critical distance between non-corresponding vias and lines can lead to problems in a device such as shorting, poor electrical yield, and low reliability. Accordingly, it may be desirable to overcome the deficiencies and limitations described hereinabove.